1. Field of the Invention
The present invention relates in general to the field of signal processing, and more specifically to a system and method that includes a gate-boosted, variable voltage supply rail amplifier.
2. Description of the Related Art
Electronic systems often include amplifiers. In general, amplifiers change power and/or amplitude of a signal Amplifiers are used in a large variety of applications, such as audio applications. A variety of amplifier designs exist. Amplifiers are often classified according to the amplifier's input and output properties, such as class A, class B, class AB, and so on. A class A amplifier is generally inefficient because a class A amplifier is always conducting, even with no input signal. Class B amplifiers amplify only one-half of an input signal wave form. Class B amplifiers are often combined into a push-pull pair. However, class B push-pull pairs often experience cross-over distortion where the two wave form halves of the push-pull pair join. Class AB amplifiers are similar to class B push-pull pairs except that class AB amplifiers always conduct.
An amplifier is most efficient when the peak-to-peak voltage swing of an output signal is equal to the amplifier supply voltage rails. The voltage “swing” refers to a maximum voltage that a signal can achieve prior to clipping of the signal. Class H control increases the efficiency of an amplifier efficiency by varying supply voltage rails so that peak output signal voltages are closer to the supply voltage rails. Class H control can be applied to any amplifier class.
FIG. 1 depicts an electronic system 100 with a class AB amplifier 102 and class H controller 120. The amplifier 102 is wholly fabricated on a semiconductor chip referred to herein as integrated circuit 104. The integrated circuit 104 includes a double-ended amplifier 106 that converts complementary voltage input signals VIN+ and VIN− into signals i− and i+. The complementary signals i− and i+ are voltage level shifted by respective NMOS and PMOS gate drive level shifters 108 and 110. “NMOS” stands for n-channel metal oxide semiconductor, and “PMOS” stands for p-channel metal oxide semiconductor. The level shifters 108 and 110 shift the direct current (DC) voltage bias of signals i− and i+ and reverse direction of signals i− and i+ but do not provide current gain. The current of signal i+ is subtracted from current iq at the gates of PMOS field effect transistors (FETs) Q1 and Q2. The current iq is subtracted from the signal i− at the gates of NMOS FETs Q3 and Q4. Current iq is supplied by respective constant current sources 112 and 114.
FIG. 2 depicts voltage waveform 202 and waveform 204 representing respective gate voltages. Referring to FIGS. 1 and 2, waveform 202 represents the gate voltage VG12 of FETs Q1 and Q2. Waveform 204 represents the gate voltage VG34 of FETs Q3 and Q4. The gate voltage VG12 and, thus, the gate-to-source voltage VGS12 of FETs Q1 and Q2 increases as signal i+ increases. The gate voltage VG34 and, thus, the gate-to-source voltage VGS34 of FETs Q3 and Q4 increases as signal i− increases.
Electronic system 100 includes a charge pump 116. Charge pump 116 is a power supply that provides supply voltage rails VDD_classB and VSS_classB. Because of the potential power demands by load 122, capacitors used by charge pump 116 are too large to be efficiently fabricated on-chip as part of integrated circuit 104. Load 122 can be any load, such as an audio speaker. So, charge pump 116 includes an off-chip capacitor network 118 to provide the capacitors used by charge pump 116. The off-chip capacitor network 118 is connected to integrated circuit 104 via pins 124 and 126.
Electronic system 100 also includes a class H controller 120 to control the voltage levels of supply voltage rails VSS_classB and VDD_classB generated by charge pump 116. For example, for a tri-mode charge pump, charge pump 116 generates output voltages +/−VCP, +/−VCP/2, and +/−VCP/3. VDD_classB equals+VCP/N, and VSS_classB equals −VCP/N, where N is an integer ranging from 1 to 3 for a tri-mode charge pump. Class H controller 120 receives input signals Vin+ and Vin− and determines a value of N based on the value of output voltage VOUT corresponding to input signals Vin+ and Vin−. Class H controller 120 generates control signal NSELECT to control the mode of charge pump 116. Class H controller 120 provides control signal NSELECT to charge pump 116. Control signal NSELECT represents the value of N. Class H controller 120 receives as inputs, input signals. Class H controller 120 sets the value of N to the minimum possible value for a given level of output signal VOUT. For example if the swing of output voltage VOUT is less than ±VCP/3, class H controller 120 sets N equal to 3. If the swing of output voltage VOUT is greater than ±VCP/3 but less than ±VCP/2, class H controller 120 sets N equal to 2. If the swing of output voltage VOUT is greater than ±VCP/2, the class-H controller 120 sets N equal to 1. Thus, efficiency of the class H controlled amplifier is better than class AB amplifiers alone because by lowering the supply voltage rails, efficiency of amplifier 102 increases because amplifier 102 delivers more power to load 122 rather than being wasted as voltage drops across FETs Q2 and Q4. Maximum efficiency is achieved when the swing of output signal VOUT is equal to the voltage between voltage supply rails VDD_classB and VSS_classB.
Electronic system 100 also includes class AB controller 121. Class AB controller 121 is connected to the drains of transistors Q1 and Q2 and controls conductivity of transistors Q1 and Q2 so that amplifier 102 operates as a class AB amplifier.
Higher power applications generally require thicker deposited gate oxide layers. Thus, as power demands by load 122, electronic system 100 is fabricated with thicker gate oxides for FETs Q2 and Q4. Thicker gate oxides increase the threshold voltage VTH of FETs Q2 and Q4. The overdrive voltage VOV equals VGS−VTH. Thus, as the threshold voltage VTH increases, for a given set of voltage supply rails VDD_classB and VSS_classB, the overdrive voltage VOV available for FETs Q2 and Q4 decreases. Increases in the signal swing of output voltage VOUT correspond to larger overdrive voltage VOV demands. Charge pump 116 is designed to provide sufficient supply voltage rails VDD_classB and VSS_classB for anticipated swings of output voltage VOUT. Because, maximum efficiency is achieved when the swing of output signal VOUT is equal to the voltage between voltage supply rails VDD_classB and VSS_classB, the gate voltages VG12 and VG34 of FETs Q2 and Q4 are limited to voltage supply rails VDD_classB and VDD_classB, which also limits the overdrive voltage VOV.
For example, if the maximum charge pump 116 output voltage VCP is 1.8V, ±VCP/3=±0.6V, and the gate voltage VG12 can only go down −VCP/3. Thus, the maximum gate-to-source voltage VGS12 is 1.2V. For a 5V, thick oxide FET Q2, the maximum overdrive voltage of FET Q2 is approximately 200 mV. Thus, for N=3, VDD_classB=600 mV, and VSS_classB=−600 mV, the swing of output signal VOUT is limited to approximately +/−250 mV before class H controller 120 switches N from 3 to 2.
FIG. 3 depicts a variable voltage supply rail plot 300 over time for various swing levels of output voltage VOUT. The value of N generated by class H controller 120 tracks the swing of output signal VOUT causing charge pump 116 to generate voltage supply rails VDD_classB and VSS_classB to track the swing of output voltage VOUT. The value of N generated by class H controller 120 tracks the swing of output signal VOUT. Until time t0, N class H controller 120 sets N equal to 3. The swing of output voltage VOUT increases, and at time t0, class H controller 120 sets N equal to 2. At time t1, class H controller 120 sets N equal to 3. The maximum available overdrive voltage VOV prevents the output voltage VOUT from reaching the supply voltage rails VDD_classB and VSS_classB. Values of N greater than 3 do not work because of limitations in the maximum overdrive voltage VOV.